Memory cells which have members that may be electrically charged are well-known in the prior art. Most often, these cells employ polysilicon floating gates which are completely surrounded by insulation (e.g., silicon dioxide). A charge is transferred to these floating gates through a variety of mechanisms such as avalanche injection, channel injection, tunnelling, etc.
The charge on the floating gate affects the surface channel conductivity in the cell. If the conductivity is above a certain level, the cell is deemed to be programmed in one binary state, and if the conductivity is below another level, it is deemed to be programmed in the other binary state. These memory cells take a variety of forms in the prior art, some being both electrically erasable and electrically programmable and others requiring, for example, ultraviolet light for erasing. The cells are incorporated into memories referred to in the prior art as EPROMs, EEPROMs, flash EPROMs and flash EEPROMs.
One of the most critical dielectrics for charge retention in an EPROM cell is the interpoly dielectric. This dielectric functions to insulate the floating gate (which is formed as a first polysilicon layer) from the control gate (which is usually formed as a second polysilicon layer) for charge storage purposes.
By way of example, during programming of an EPROM device the control gate is taken to a high positive potential ranging between 12-20 volts. When this high programming potential is supplied to the control gate the interpoly dielectric must be sufficiently strong (i.e., a high breakdown voltage) to block the Fowler-Nordheim (FN) tunneling of electrons from the floating gate to the control gate to prevent charge loss. Charge loss is a major reliability problem in EPROM-related devices.
Concurrent with the need to effectively isolate the floating gate from the control gate is the desire to scale or shrink the device as small as possible to increase overall circuit density. As is done in conventional transistor scaling, dielectrics are typically thinned to improve the performance of electrically programmable memories. Recall that the interpoly dielectric forms a capacitor in series with the gate capacitance. Any voltage applied to the control electrode will be capacitively shared with the floating gate electrode. For a given control gate voltage the capacitive coupling determines the voltage seen on the floating gate and thus the electrical performance of the transistor. Therefore, a very thin dielectric provides optimum transistor performance from a capacitance coupling perspective.
Thin dielectrics, however, have been the source of many problems in prior art processes. Chief among them is the fact that a thin dielectric presents a smaller potential barrier to electrons attracted to the positively-charged control gate.
The present invention provides a reliable interpoly dielectric which overcomes the problems of intrinsic charge loss in EPROM devices. The electrical properties of the invented dielectric structure allow a substantial capacitance increase for a given horizontal capacitor dimension (e.g., the floating gate and/or control gate dimension). This increased capacitance enhances the capacitive coupling between the control gate and the floating gate while providing greater charge retention than previous methods.
As will be seen, the invented structure is characterized by a relatively thick, chemically deposited (CVD) oxide film on top of an underlying nitride layer. Under a positive control gate potential, the thick CVD oxide provides a higher breakdown voltage than prior art approaches. The physical mechanism responsible for differences in positive versus negative carrier blocking potential is explained in an article entitled "Determination of the Fowler-Nordheim Tunneling Barrier from Nitride to Oxide in Oxide: Nitride Dual Dielectric", by Leo D. Yau, IEEE Electron Device Letters, Vol. EDL-7, No. 6, June, 1986; pp. 365-367.